JPS6228874B2 - - Google Patents
Info
- Publication number
- JPS6228874B2 JPS6228874B2 JP54043774A JP4377479A JPS6228874B2 JP S6228874 B2 JPS6228874 B2 JP S6228874B2 JP 54043774 A JP54043774 A JP 54043774A JP 4377479 A JP4377479 A JP 4377479A JP S6228874 B2 JPS6228874 B2 JP S6228874B2
- Authority
- JP
- Japan
- Prior art keywords
- test
- pattern
- expected value
- input
- main memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4377479A JPS55135762A (en) | 1979-04-11 | 1979-04-11 | Ic test unit |
US06/069,345 US4313200A (en) | 1978-08-28 | 1979-08-24 | Logic test system permitting test pattern changes without dummy cycles |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4377479A JPS55135762A (en) | 1979-04-11 | 1979-04-11 | Ic test unit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55135762A JPS55135762A (en) | 1980-10-22 |
JPS6228874B2 true JPS6228874B2 (en]) | 1987-06-23 |
Family
ID=12673091
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4377479A Granted JPS55135762A (en) | 1978-08-28 | 1979-04-11 | Ic test unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55135762A (en]) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4502127A (en) * | 1982-05-17 | 1985-02-26 | Fairchild Camera And Instrument Corporation | Test system memory architecture for passing parameters and testing dynamic components |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5585265A (en) * | 1978-12-23 | 1980-06-27 | Toshiba Corp | Function test evaluation device for integrated circuit |
-
1979
- 1979-04-11 JP JP4377479A patent/JPS55135762A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS55135762A (en) | 1980-10-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100488232B1 (ko) | 집적 dma 제어기를 이용한 집적 메모리 테스트 방법 | |
US4404519A (en) | Testing embedded arrays in large scale integrated circuits | |
US20020071325A1 (en) | Built-in self-test arrangement for integrated circuit memory devices | |
US6353563B1 (en) | Built-in self-test arrangement for integrated circuit memory devices | |
US4402081A (en) | Semiconductor memory test pattern generating apparatus | |
JPS60130839A (ja) | テスト装置 | |
JPS62266638A (ja) | デイジタルデ−タを記憶するための複数個のメモリ場所の各々の機能性をテストする方法 | |
US20040093539A1 (en) | Method for testing embedded DRAM arrays | |
JPS6288972A (ja) | 階層テスト・シ−ケンサ | |
JPH02255925A (ja) | メモリテスト方法および装置 | |
KR100351768B1 (ko) | 벡터모듈테이블을사용하는자동테스트장치용메모리아키텍처 | |
JPH10112199A (ja) | メモリ試験装置 | |
JP2591825B2 (ja) | 圧縮データを用いた論理回路試験方法及びその装置 | |
KR940002904B1 (ko) | 데이타 처리 시스템 및 이 시스템에 있어서의 다수 메모리 어레이 테스팅 방법 | |
JP2001273794A (ja) | フェイル前情報取得回路およびその取得方法 | |
JPS6228874B2 (en]) | ||
EP0263312A2 (en) | Semiconductor memory device with a self-testing function | |
JP3819056B2 (ja) | ベクトル・モジュール・テーブルを用いる自動テスト装置のためのメモリ・アーキテクチャ | |
US6430096B1 (en) | Method for testing a memory device with redundancy | |
GB2235074A (en) | Testing a memory device | |
JPS63148498A (ja) | 自己診断機能を具備した記憶装置 | |
JP3102600B2 (ja) | Icテスタ | |
JPS59101100A (ja) | 記憶装置の試験方式 | |
JPS585681A (ja) | 半導体メモリ試験装置 | |
JPH0249520B2 (en]) |